1 features ? 16-bit fixed-point digital signal processing (dsp) core low-power consumption: ? atc35/atl35 - 2 mw/mips at 3.3v ? atc25/atl25 - 1 mw/mips at 2.5v ? atc20/atl20 - 0.6 mw/mips at 1.8v high performance: ? atc35/atl35 - 52 mips, 104 mhz at 3.0v/85 c (worst case) ? atc25/atl25 - 70 mips, 140 mhz at 2.25v/85 c (worst case) ? atc20/atl20 - 65 mips, 130 mhz at 1.6v/85 c (worst case) small die size: ? atc35/atl35 - 2.5 mm 2 ? atc25/atl25 - 1.3 mm 2 ? atc20/atl20 - 1.3 mm 2 slow mode and stop mode allow further power reduction wide range of operating voltage: 1.8v - 3.6v high level of modularity: ? expandable data and program ram and/or rom ? user-definable registers 64k x 16-bit data address space, 64k x 16-bit program address space three parallel execution units wait states are supported to link with slow external devices advanced windows-based development tools: macro assembler, linker, c compiler, debugger (emulator, simulator) optional ?on-core emulator? allows the on-core debugger, embedded in the asic, to be run jtag serial interface for on-chip debug (optional) description atmel?s embedded OAKDSPCORE ? is a 16-bit general-purpose low-power, low-voltage and high-speed digital signal processor (dsp). it is designed for mid-to-high-end tele- communications and consumer electronics applications, where low power and portability are major requirements. among the applications supported are digital cellu- lar telephones, fast modems, advanced facsimile machines and hard disk drives. OAKDSPCORE is available as a dsp core in atmel?s standard cell library, to be utilized as an engine for dsp-based asics. it is specified with several levels of modularity in ram, rom and i/o blocks, allowing efficient dsp-based asic development. OAKDSPCORE is aimed at achieving the best cost-performance factor for a given (small) silicon area. as a key element of a system-on-chip, it takes into account such requirements as program size, data memory size, glue logic, power management, etc. the OAKDSPCORE consists of three main execution units operating in parallel: the computation/bit manipulation unit (cbu), the data address arithmetic unit (daau) and the program control unit (pcu). the core also contains rom and ram address- ing units, and program control logic (pcl). all other peripheral blocks, which are application specific, are defined as a part of the user-specific logic, implemented around the dsp core on the same silicon die. OAKDSPCORE has an enhanced set of dsp and general microprocessor functions to meet the application requirements. the OAKDSPCORE programming model and instruction set are aimed at straightforward generation of efficient and compact code. embedded digital signal processing core OAKDSPCORE ? rev. 0876e?03/00
2 figure 1. symbol signal description OAKDSPCORE on-core memory gixdpp<15:0> docxap<10:0> rxsp<15:0> dyan<10:0> rydp<15:0> docxa10n drxrm1p dwxrm1p doexrm1p drxrm2p dwxrm2p doexrm2p pmemenp dya10n dryrm1p dwyrm1p doeyrm1p dryrm2p dwyrm2p doeyrm2p omemsz4p gexdbp<15:0> dxap<15:0> pedwp pedrp pesrcn<5:0> pedstn<5:0> gip<15:0> ppap<15:0> pprp ppwp pextip bextpp prwextp dofctrp bfloatdp bfloatpp biuser0p biuser1p cusero0p cusero0p piackn lint0p lint1p lint2p inmip btrapreqp pstatusp<3:0> ptrapap pbkendp ddtvmp psftp pdummyp bwaitp bbootp phi1 phi2 lrstp system ocem interrupts user i/o dma program memory off core memory table 1. on-core memory signal name width description input signals rydp <15:0> 16 yram data bus omemsz4p 1 memory size 4k rxsp <15:0> 16 xram data bus input/output signals gixdbp <15:0> 16 internal data bus output signals dyan <10:0> 11 on-core yram address dya10n 1 on-core yram address - bit 10 dryrm1p 1 on-core yram read (lower 1k) dwyrm1p 1 on-core yram write (lower 1k) doeyrm1p 1 on-core yram output enable (lower 1k) dryrm2p 1 on-core yram read (upper 1k) dwyrm2p 1 on-core yram write (upper 1k) doeyrm2p 1 on-core yram output enable (upper 1k) docxap <10:0> 11 on-core xram address docxa10n 1 on-core xram address - bit 10 drxrm1p 1 on-core xram read (lower 1k) dwxrm1p 1 on-core xram write (lower 1k) doexrm1p 1 on-core xram output enable (lower 1k) drxrm2p 1 on-core xram read (upper 1k) dwxrm2p 1 on-core xram write (upper 1k) doexrm2p 1 on-core xram output enable (upper 1k) pmemenp 1 data memory enable
3 table 2. off-core memory signal name width description input/output signals gexdbp <15:0> 16 external data bus output signals pesrcn <5:0> 6 source bus pedstn <5:0> 6 destination bus dxap <15:0> 16 off-core xram address pedwp 1 data write pedrp 1 data read table 3. program memory signal name width description input signals bextpp 1 external program indication input/output signals gip <15:0> 16 instruction data output signals pextip 1 movp instruction indication ppap <15:0> 16 program address pprp 1 program read ppwp 1 program write table 4. direct memory access (dma) signal name width description input signals bfloatdp 1 float dxap bus control bfloatpp 1 float ppap bus control output signals prwextp 1 read or write to/from external registers dofctrp 1 off core data transaction table 5. user i/o signal name width description input signals biuser0p 1 user input 0 biuser1p 1 user input 1 output signals cusero0p 1 user output 0 cusero1p 1 user output 1 table 6. interrupts signal name width description input signals lint0p 1 interrupt 0 lint1p 1 interrupt 1 lint2p 1 interrupt 2 lnmip 1 non-maskable interrupt output signals piackn 1 interrupt acknowledge table 7. on-chip emulation module (ocem) signal name width description input signals btrapreqp 1 trap interrupt output signals pstatusp <3:0> 4 internal status (used by the ocem module) ptrapap 1 trap active indication pbkendp 1 block repeat end ddtvmp 1 data value match psftp 1 software trap indication pdummyp 1 dummy fetch (used by the ocem module) table 8. system signal name width description input signals phi1 1 phase1 clock phi2 1 phase2 clock lrstp 1 reset bwaitp 1 wait state indication bbootp 1 boot indication table 5. user i/o (continued) signal name width description
4 OAKDSPCORE architecture the OAKDSPCORE consists of three main execution units operating in parallel: the computation/bit manipulation unit (cbu) the data address arithmetic unit (daau) the program control unit (pcu) the OAKDSPCORE also supports four user-definable regis- ters, enabling future expansion of the core residing in off- core glue logic. the user defined registers are part of the core register set, meaning that they can be accessed by most oak instructions. figure 2. OAKDSPCORE block diagram note: x- and y-ram sizes depend on the customer ? s need. the variable size minimizes overhead area. bmu cu cbu pcu barrel shifter bfo b-accumulator 0 b-accumulator 1 multiplier alu accumulator 0 accumulator 1 daau x-ram on-core memory y-data bus y-address bus x-data bus x-address bus user defined register stack-pointer y-ram status registers reset bpi int0 int1 int2 nmi program address bus program data bus
5 computation/bit manipulation unit the computation/bit manipulation unit (cbu) contains three main elements: the computation unit (cu) the bit manipulation unit (bmu). the saturation unit, which is shared by the cu and the bmu units. figure 3. computation and bit manipulation unit block diagram the cu consists of a 16- by 16-bit parallel 2s complement multiplier, supporting single and double precision multiplication, a 36-bit arithmetical and logical unit (alu) and two 36-bit a-accumulators with access to the two additional b-accumulators of the bmu. the OAKDSPCORE can perform a single-cycle multiply-accumulate (mac) instruction, and has support for double precision multiplication. a single-cycle division step is supported. the arithmetic logic unit (alu) performs all arithmetic and logical operations on data operands. it is a 36-bit, single- cycle, non-pipelined unit. a maximum or minimum opera- tion is available. the bmu consists of a full 36-bit barrel shifter, a bit-field operation (bfo) unit, a special hardware (exp) for exponent calculation, and two 36-bit b-accumulators with access to the two a-accumulators of the cu. extension nibbles of the b-accumulators offer protection against 32- bit overflows. the shift value (sv) register is a 16-bit register used for shifting operation and exponent calculation. context switching (swapping) between the two sets of accumulators is supported. saturation arithmetic is provided to selectively limit over- flow from the high portion of an accumulator to the extension bits. when necessary the saturation logic substi- tutes a limited data value having maximum magnitude and the same sign as the source accumulator. scaling shifter multiplier alu mux x y p accumulator a0 accumulator a1 accumulator b0 accumulator b1 swap saturation unit exp sv barrel shifter bit manipulation unit computation unit y data bus x data bus bit field operation
6 data address arithmetic unit the data address arithmetic unit (daau) performs all address storage and effective address calculations neces- sary to address data operands in data and program memories. it also supports the software stack pointer. this unit operates in parallel with other core resources to mini- mize address generation overhead. the daau contains six 16-bit address registers for indirect addressing, two 16-bit configuration registers for modulo and increment or decre- ment step control, and a base register for supporting index addressing. in addition, it contains a 16-bit stack pointer register and four alternative bank registers that are sup- ported by an individual bank exchange. a 16-bit minimum and maximum pointer latching register also is contained. the daau can generate two 16-bit addresses every instruction cycle. these can be post-modified by two modi- fiers: linear and modulo modifier. the address modifiers allow the creation of data structures in memory for circular buffers, delay lines, fifos, another pointer to the software stack, etc. program control unit the program control unit (pcu) performs instruction fetch, instruction decoding, exception handling, hardware loop control, wait state support and on-chip emulation support. in addition, it controls the internal program memory protection. the pcu contains the repeat and block-repeat unit, and two 16-bit directly accessible registers: the program counter and the loop counter of the block-repeat unit. instruction set the oak instruction set is balanced between dsp and control functions, thus permitting both dsp and high-speed control activities. there are a total of 89 instructions. all have been carefully designed to produce compact code. the OAKDSPCORE has an internal four-stage pipeline which continually performs concurrent instruction fetch, decode fetch, operand fetch and instruction execution. this allows instruction execution to overlap, thus the effective execution time for most instructions is one cycle. of particular significance are the repeat and block repeat (four nested levels) capabilities. this instruction set optimizes the OAKDSPCORE for algo- rithms such as viterbi decoding, adaptive filtering, and cellular phone applications. on-chip emulation the OAKDSPCORE has the capability to be combined with an on-chip emulation module (ocem). the ocem pro- vides hardware emulation and program flow trace buffering. hardware emulation allows breakpoints due to a pre-defined condition such as program or data address match, single stepping, etc. program flow buffer records, during run time, those instruc- tion addresses that cause a non-continuity in the program flow. these addresses are kept in a fifo within the ocem block and used afterwards to re-construct the complete program flow graph. development tools development tools are a critical element in core-based asic design as they affect the design cycle and the time- to-market. for ease of development of dsp-based applica- tions, the OAKDSPCORE is supplied with a comprehensive set of hardware and software tools, and a development platform for rapid prototyping. these feature a familiar design technology, full-speed and real-time emulation/sim- ulation, easy of use and interactivity. hardware development tools the OAKDSPCORE hardware tools include the odkit stand- alone board, odkit accelerator, and the combo debug interface (cdi). the odkit/cdi is a unified line of develop- ment tools which provides the user the ability to develop and debug an application-specific oak-based system in the same software environment. the odkit also has a reduced version called the accelera- tor. the accelerator provides the user the ability of very fast turn-key development of firmware (and application specific software) as well as a hardware acceleration engine for heavy simulations. the accelerator doesn ? t provide a pro- totyping ability. the stand-alone odkit provides the user an ability of fast prototyping of application specific hard- ware. so three different products are established in the product line: the accelerator, the stand-alone odkit and the cdi. the last two devices use an isa extender card for the pc host link, while the accelerator must be plugged into an isa bus connector of the host pc. the odkit is designed for prototyping during combo (oak based asic) development stage, whereas the cdi is designed for combo debug and/or re-targeting stages. both devices support a stand-alone (demo mode) opera- tion. both the stand-alone odkit and odkit accelerator card include an oak development chip, program and data mem- ory, boot logic, eprom socket, dual-ported monitor
7 mailbox memory, and codec with audio input and out- put connectors. the cdi contains the pc isa host interface, dual-ported monitor mailbox memory, program memory, eprom socket, boot logic, c-bus interface and target connector interface. it does not include the oak development chip or oak socket like the odkit boards. the cdi would be used for hardware verification/debug of an oak based asic or assp that has a different package than the oak develop- ment chip. software development tools the OAKDSPCORE command line software tools include a coff macro assembler and linker, and ansi c compiler. the gui based tools include the coff symbolic debugger and assyst simulator. the assyst simulator is used to simulate external hardware in simulation mode before actual target hardware is available. the debugger can operate in either emulation or simulation modes on a pc, depending upon whether oak-based tar- get hardware is attached. the debugger supports source level debugging in assembly, c/c++, or mixed assembly and c/c++ modes. it also includes a disassembler, an in- line assembler, and an application profiler. in simulation mode the application profiler indicates memory usage, pro- gram flow, instruction usage, real time consumption and more. the software tools are available for windows 3.1, windows ? 95, and windows nt ? operating systems. as a unix/motif compatible application, it can run on sun sparc workstations in simulation mode only. figure 4. windows user interface of the oak development kit
? atmel corporation 2000. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard war- ranty which is detailed in atmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any tim e without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectu al prop- erty of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel (408) 441-0311 fax (408) 487-2600 europe atmel u.k., ltd. coliseum business centre riverside way camberley, surrey gu15 3yl england tel (44) 1276-686-677 fax (44) 1276-686-697 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 atmel colorado springs 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 tel (719) 576-3300 fax (719) 540-1759 atmel rousset zone industrielle 13106 rousset cedex france tel (33) 4-4253-6000 fax (33) 4-4253-6001 fax-on-demand north america: 1-(800) 292-8635 international: 1-(408) 441-0732 e-mail literature@atmel.com web site http://www.atmel.com bbs 1-(408) 436-4309 printed on recycled paper. 0876e ? 03/00/xm marks bearing ? and/or ? are registered trademarks and trademarks of atmel corporation. OAKDSPCORE is a registered trademark of dsp group, inc. windows amd windows nt are registered trademarks of microsoft corp. terms and product names in this document may be trademarks of others.
|
